Present complementary metal oxide semiconductor (CMOS) circuits are frequently used for a variety of computer applications including lap top and notebook computer systems which are battery powered. These applications impose practical limitations such as speed, power, and feature size on semiconductor design. Optimal performance of a system depends on an effective balance of these factors.
Input buffers in semiconductors such as dynamic random access memories (DRAM) act as an interface between external input signals and internal logic circuits. Input buffer designs, as disclosed in FIGS. 126, 138, and 139 of U.S. Pat. No. 5,208,776, entitled PULSE GENERATION CIRCUIT, translate external transistor-transistor logic (TTL) logic level signals to internal logic level signals. These TTL input buffers are designed to minimize operating power consumption during a standby mode. However, they are sensitive to transistor threshold voltage variation. Therefore, TTL input buffer speed degrades significantly with variations in operating voltage and temperature. Furthermore, the ability of the TTL input buffer to correctly determine an external input signal level may degrade significantly due to internal noise on supply voltage bus lines during an active mode.
Differential input buffers disclosed in U.S. Pat. No. 4,280,070, entitled BALANCED INPUT BUFFER CIRCUIT FOR SEMICONDUCTOR MEMORY, and U.S. Pat. No. 4,288,706, entitled NOISE IMMUNITY IN INPUT BUFFER CIRCUIT FOR SEMICONDUCTOR MEMORY, compare external logic signals to a stable internal reference signal to produce an internal logic level signal. These differential input buffers offer greater speed and noise immunity than TTL input buffers. However, use of differential input buffers greatly increases operating power consumption during a standby mode.